Handling Expected-data-transfer-legnth and CDB transfer-len mismatch
2007-05-14 21:29:43 GMT
We saw an initiator problem where the expected-data-transfer-length and transfer-len inside CDB got mismatched for a write-and-verify (10). The expected-data-transfer-length is 0x4000 but the transfer-len in the CDB is 0. The target completed the request with good status, turned Residual-underflow bit on and set residual-count=0x4000. See frames 16 and 38 in the attached ethereal trace file for details. Did the target handle this error condition correctly?
Engenio Storage Group - LSI Logic
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