3 Feb 2006 09:20
Re: PostgreSQL
Johnny Billquist <bqt <at> update.uu.se>
2006-02-03 08:20:04 GMT
2006-02-03 08:20:04 GMT
Vincent wrote: > Johnny Billquist a écrit : > >> Yes, I took a rather restricted view. >> I was talking (and thinking) about the bus transactions, not machine >> language (or some even higher language constructs). > > There are been some good answers over "what is" a write. Just to add one > thing that have been overlooked: cache. Normal writes goes on the cache, > nowdays. 68020/68030 had a write-through cache, but most of the modern > processors operate in write-back mode. That means that a write can be > much of complex thing, invalidating lines in many other peers (snoop > operation). True. And also, with a writeback cache, it ususally perform aligned full word writes for you, once it decides to write the data back. > However, a r/m/w locked instruction should always be performed in > write-through mode, in order to avoid the overhead of changing other's > cache status. Semaphores should not be cached. Um no.You have to invalidate other CPUs caches when doing a write. Even on a r/m/w which is interlocked. Semaphores definitely should not be cached, but the cache system don't know we're talking about a semaphore. It's all just memory. So unless you can guarantee that other CPUs don't cache the memory location at all, you'll need to change other CPUs cache. (Well, actually, I know of atleast one CPU which have a specific instruction which always bypass the cache totally, which is used for mutex locks, so on that machine the cache can be left alone. But I think that's an exception.) Johnny -- -- Johnny Billquist || "I'm on a bus || on a psychedelic trip email: bqt <at> update.uu.se || Reading murder books pdp is alive! || tryin' to stay hip" - B. Idol
You have to invalidate other CPUs caches when doing a write. Even on a
r/m/w which is interlocked. Semaphores definitely should not be cached,
but the cache system don't know we're talking about a semaphore. It's
all just memory. So unless you can guarantee that other CPUs don't cache
the memory location at all, you'll need to change other CPUs cache.
(Well, actually, I know of atleast one CPU which have a specific
instruction which always bypass the cache totally, which is used for
mutex locks, so on that machine the cache can be left alone. But I think
that's an exception.)
Johnny
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