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Re: what level of overshoot is acceptalbe

How exactly are you measuring the overshoot? Active probes? Or is this just in simulation.

-Hithesh

-----Original Message-----
From: si-list-bounce@...
[mailto:si-list-bounce@...] On Behalf Of WANG Zhenwei
Sent: Thursday, December 01, 2011 11:28 AM
To: ERIK KUNDRO; si-list@...
Subject: [SI-LIST] Re: what level of overshoot is acceptalbe

Hi Erik,
    i very understand. my boss want a warrant that no different between primary chip and the secondary chip,
espectially in SI. but the measurement on overshooting exceeds 25%, which peak is exceed to 4V(flash was
power 3.3V). the result is very bad. so my question is what level of overshoot is acceptable? that is the history.

BR

Zhenwei Wang

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From: ERIK KUNDRO [mailto:kundro85@...] 
Sent: 2011Äê12ÔÂ1ÈÕ 13:49
To: si-list@...; WANG Zhenwei
Subject: RE: [SI-LIST] what level of overshoot is acceptalbe

I guess you can look at it as 12% above Vcc. Just be careful not to assume its always 12%. If your Vcc was
slightly less or slightly more... it could be 10% or 13% because the ration relative to 0.4V would change.

Basically, if your Vcc is 3.3V, then you can experience up to 3.7V of overshoot for no more than 20ns. Very
important to keep the 20ns in mind. If you see 3.7000V last for 21ns, then its too much. If you cross the 3.7V
threshold, even for an instant, then you violate the spec...

Ideally, you should not go above VIH, which you said was Vcc+0.3V or in this case 3.6V assuming a Vcc of 3.3V. I
always like to be conservative like that.

Keep in mind that overshoot can vary from board to board and part to part depending on processes variance of
the IO drivers. So if you are close already, I would take steps to remove the overshoot because the next
board or part could have more or less overshoot.

If you are getting overshoot on some signals, add series resistors at the signal source to squelch the
overshoot. You may have to play around with the resistor value (I'd start with 25¦¸), but at some point
that resistor should remove the overshoot and you should get a near textbook waveform. If you have a signal
integrity simulation tool, you can get the IBIS models and simulate the interface while experimenting
with various series resistor values. Just be aware that the series resistors may slow down the rising
edges of the signal and cause timing errors if you slow them down too much.

Erik M. Kundro

--- On Wed, 11/30/11, WANG Zhenwei
<Zhenwei.Wang@...> wrote:

	From: WANG Zhenwei <Zhenwei.Wang@...>
	Subject: RE: [SI-LIST] what level of overshoot is acceptalbe
	To: "ERIK KUNDRO" <kundro85@...>, si-list@...
	Date: Wednesday, November 30, 2011, 10:51 PM
	
	
	Hi Rrik,
	    thanks for quick response. if i am not misunderstanding you description, the acceptable overshoot is
less than 0.4V/vcc, which is 0.4v/3.3v% in my project. am i right? 
	 

	BR 

	Zhenwei Wang

	

	

	
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________________________________

	From: ERIK KUNDRO [mailto:kundro85@...] 
	Sent: 2011Äê12ÔÂ1ÈÕ 10:50
	To: si-list@...; WANG Zhenwei
	Subject: Re: [SI-LIST] what level of overshoot is acceptalbe
	
	
Hello,

I think you are over thinking the problem. The spec says max overshoot is vcc+ 0.4V for 20ns or less. Vcc being
the actual Vcc the part is seeing at the moment of overshoot... NOT the max the part can tolerate. 

So, if your Vcc at the part is 3.3V, then the max overshoot your can tolerate is 3.3V+0.4V=3.7V. For 20ns or
less. The instant you cross the 3.7V threshold, you violate the spec... not matter how brief.

If your Vcc at the part is 3.4V, then the max overshoot your can tolerate is 3.4V+0.4V=3.8V. For 20ns or
less.The instant you cross the 3.8V threshold, you violate the spec... not matter how brief.

If your Vcc at the part is 3.0V, then the max overshoot your can tolerate is 3.0V+0.4V=3.4V. For 20ns or
less.The instant you cross the 3.4V threshold, you violate the spec... not matter how brief.

Call the manufacturer of the part for clarification if you are not sure how to interpret this. An FAE should
be able to get you the answer.  

Erik M. Kundro

--- On Wed, 11/30/11, WANG Zhenwei
<Zhenwei.Wang@...> wrote:

	From: WANG Zhenwei <Zhenwei.Wang@...>
	Subject: [SI-LIST] what level of overshoot is acceptalbe
	To: si-list@...
	Date: Wednesday, November 30, 2011, 8:13 PM
	
	
	Hi guys,
	         I have a problem: what level of overshoot is acceptable? I was
	ordered to qualify a new nand flash on my project. There are an signal
	integrity measurement on overshooting. Some info form spec of nand:
	
	1. power supply:3.3V, so the ideal logic high is 3.3V. 
	
	2. max power : 3.6V
	
	3. Input High Voltage VIH:  2.0~ VCC +0.3;  Input Low Voltage VIL,
	-0.3~0.8
	
	3. NOTE : 1) VIL can undershoot to -0.4V and VIH can overshoot to VCC +
	0.4V for durations of 20 ns or less.
	
	         So my formula is :
	
	         The max acceptable overshoot=(max power + 0.4V )/( ideal logic
	high )=(3.6V + 0.4V)/3.3V!%.
	
	        Am I right?
	
	BR
	
	Zhenwei Wang
	
	
	
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